The present invention relates generally to semiconductor devices and particularly to the fabrication of relatively high value polysilicon resistors for use in static random access memory cells.
Single event upset (SEU) is a phenomenon in which a localized photo-current pulse is produced by a charged particle incident on the sensitive node of a storage element or memory cell causing it to upset when the collected charge is larger than the critical charge for upset. An effective method to reduce susceptability to SEU is to increase the critical charge required for upset by placing large cross-coupling resistors in the storage element to increase the RC time constant delay associated with the gate capacitances of the transistors of the storage element. These cross-coupling or SEU resistors have typically been polysilicon implanted with arsenic, boron or phosphorus ions to achieve a desired resistivity. One example of the variation of measured resistivity values at 25.degree. C. for polysilicon having an arsenic implant at 60 Kev and dose ranging from 2.times.10.sup.14 to 8.times.10.sup.14 cm.sup.-2 is shown in FIG. 5.
Further background follows with reference to FIG. 1 which illustrates a conventional six transistor CMOS static memory cell, typically used in a static random access memory (SRAM). Memory cell 10 uses cross-coupled CMOS inverters. CMOS inverter 12 includes P-channel transistor 14 and n-channel transistor 16 with their source to drain paths connected in series between Vcc and ground and their gates connected together. Second CMOS inverter 18 has p-channel transistor 22 and n- channel transistor 24 having their source-to drain paths connected in series between Vcc and ground and their gates common.
The susceptability of a memory cell to upset may be reduced by increasing the critical charge of the cell. As shown in FIG. 1 resistors 20 and 30 are included in the cross coupling lines of inverters 12 and 18. Resistor 20 is connected between the common gate connection of inverter 12 and the common drain connection of inverter 18. Resistor 30 is connected between the common gate connection of inverter 18 and the common drain connection of inverter 12. SEU resistors 20 and 30 increase the RC time constant delay associated with the gate capacitances of transistors 14, 16, 22, and 24. The required resistance value for SEU resistors depends on the particular design, however resistivity values from 50 kilohm/sq. to 250 kilohm/sq. are often required. For many applications the resistivity must be reproducible for temperatures between -55.degree. and 125.degree. C. Experience with arsenic implanted polysilicon SEU resistors in this resistance range has shown variations of 50% or more in resistance values for resistors from different lots. Thus a need exists for a process of making SEU resistors that is reproducible from lot to lot or run to run of wafers.